Topics

• Planned for weeks 1, 2 and 3:
  Chapter 1 - Computer Abstractions and Technology
  1.1 Introduction
  1.2 Eight Great Ideas in Computer Architecture
  1.3 Below Your Program
  1.4 Under the Covers
  1.5 Technologies for Building Processors and Memory
  1.6 Performance
  1.7 The Power Wall
  1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
  1.9 Real Stuff: Benchmarking the Intel Core i7
  1.10 Going Faster: Matrix Multiply in Python
  1.11 Fallacies and Pitfalls
  1.12 Concluding Remarks
  
• Planned for weeks 4, 5 and 6:
  2. Instructions: Language of the Computer
  2.1 Introduction
  2.2 Operations of the Computer Hardware
  2.3 Operands of the Computer Hardware
  2.4 Signed and Unsigned Numbers
  2.5 Representing Instructions in the Computer
  2.6 Logical Operations
  2.7 Instructions for Making Decisions
  2.8 Supporting Procedures in Computer Hardware
  2.9 Communicating with People
  2.10 LEGv8 Addressing for Wide Immediates and Addresses
  2.11 Parallelism and Instructions: Synchronization
  2.12 Translating and Starting a Program
  2.13 A C Sort Example to Put it All Together
  2.14 Arrays versus Pointers
  * 2.15 Advanced Material: Compiling C and Interpreting Java
  2.16 Real Stuff: MIPS Instructions
  2.17 Real Stuff: ARMv7 (32-bit) Instructions
  2.18 Real Stuff: ARMv8 (64-bit) Instructions
  2.19 Real Stuff: x86 Instructions
  2.20 Real Stuff: The Rest of the RISC-V Instruction Set
  2.21 Going Faster: Matrix Multiply in C
  2.22 Fallacies and Pitfalls
  2.23 Concluding Remarks
  * 2.24 Historical Perspective
  
• Planned for week 7:
  Appendix A: The Basics of Logic Design
  Gates, Truth Tables, and Logic Equations
  Combinational Logic
  Clocks
  FSMs
  Memory
• Planned for weeks 8 and 9:
  3. Arithmetic for Computers
  3.1 Introduction
  3.2 Addition and Subtraction
  3.3 Multiplication
  3.4 Division
  3.5 Floating Point
  3.6 Parallelism and Computer Arithmetic: Subword Parallelism
  3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
  3.8 Going Faster: Subword Parallelism and Matrix Multiply
  3.9 Fallacies and Pitfalls
  3.10 Concluding Remarks
  * 3.11 Historical Perspective
  
• Planned for weeks 10, 11 and 12
  4. The Processor
  4.1 Introduction
  4.2 Logic Design Conventions
  4.3 Building a Datapath
  4.4 A Simple Implementation Scheme
  * 4.5 Multicycle Implementation
  4.6 An Overview of Pipelining
  4.7 Pipelined Datapath and Control
  4.8 Data Hazards: Forwarding versus Stalling
  4.9 Control Hazards
  4.10 Exceptions
  4.11 Parallelism via Instructions
  4.12 Putting it All Together: The Intel Core i7 6700 and ARM Cortex-A53
  4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply
  * 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
  4.15 Fallacies and Pitfalls
  4.16 Concluding Remarks
  * 4.17 Historical Perspective
• Planned for weeks 13 and 14:
  5. Large and Fast: Exploiting Memory Hierarchy
  5.1 Introduction
  5.2 Memory Technologies
  5.3 The Basics of Caches
  5.4 Measuring and Improving Cache Performance
  5.5 Dependable Memory Hierarchy
  5.6 Virtual Machines
  5.7 Virtual Memory
  5.8 A Common Framework for Memory Hierarchy
  5.9 Using a Finite-State Machine to Control a Simple Cache
  5.10 Parallelism and Memory Hierarchy: Cache Coherence
  * 5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
  * 5.12 Advanced Material: Implementing Cache Controllers
  5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies
  5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions
  5.15 Going Faster: Cache Blocking and Matrix Multiply
  5.16 Fallacies and Pitfalls
  5.17 Concluding Remarks