Michael Weeks

Ph.D. Dissertation,
University of Louisiana at Lafayette
May 1998

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The 3-D Discrete Wavelet Transform (DWT) suits video compression applications well, without blocking artifacts of other mehods, such as DCT. Many architectures for the Discrete Wavelet Transforms have been proposed since 1990. The DWT is not a straight-forward problem to implement on a chip, so there are several types of designs. This talks presents two new architectures for the DWT.

The first architecture is an implementation of the 3-D DWT similar to 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set doing the calculations for one dimension. The filters are easily scalable to a larger size. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times.

The second architecture uses block inputs to reduce the amount of on-chip memory. It has a control unit to select which coefficients to pass on to the low and high pass filters. The memory on the chip will be small compared to the input size, since it depends solely on the filter sizes. These two designs are the first 3-D DWT architectures.

Department: Electrical and Computer Engineering
University: University of Louisiana
Univ. location: Lafayette, Louisiana

Dissertation advisor: Dr. M. Bayoumi
Advisor's department: Electrical and Computer Engineering