CSc 4250/6250 Homework #3

This assignment is to design additional gates in Magic, and simulate gates in Spice.

First, design a 2-input AND gate, another 2-input AND gate, and a D-latch. The D-latch design may require reading ahead a bit (see the handout on memory). The first AND gate should just be a NAND gate followed by an inverter. The second AND gate should be designed just as you would design any other gate. Assume that you do not have dual-rail logic.

Use Spice software to test out your Inverter, 2-input NOR, 2-input NAND, 2-input XOR, the two 2-input ANDs, and your D-latch. Do these parts work like they should? If you find an error, re-do the gate(s) in question, and re-simulate them.

For the 2-input ANDs, does Spice indicate that one is better than the other? Justify your conclusions with graphs.

What to turn in:

• include your designs (on paper) for the second AND gate
• include your designs (on paper) for the D-latch. Cite your sources.
• include a log file where your submit the magic files to the TA
• include a log file of your spice sessions.
  Make sure to "cat" your finalized spice and ext files so that they are in the printout.
  Your log files should be "cleaned up" and printed in a monospaced font, like we discussed in class. Always keep original (non-"cleaned up") copies of your log files, too.
• include graphs generated by spice. Write on them to justify your conclusions about why your gates work. These graphs may need to be altered with a graphics editor (like xv or gimp) to be clear. That is, if the graph has a thin yellow line on a black background, it will not print well. Instead, change it to a white background, perhaps with the line color in black. Use color as appropriate, but if you do, be sure to use a color printer.
• be sure to address all of the points and questions of this homework.