CSc 4250/6250 Homework #1


Inverter, NAND, NOR, XOR


You are allowed to do this assignment alone, or with one partner. If you work with a partner, just turn in one solution, but make sure that both names are on it. I may take off points if the names are not spelled correctly!

Make the following parts using Magic software:

Make each as small as possible.

Save each gate as a separate file.

All gates should be able to share a common Vdd and GND line. (That is, if the 3 gates are placed side-by-side, a single wire in metal-1 representing Vdd could be drawn to connect all three. Likewise, another wire in metal-1 representing GND could be drawn.) Run metal-1 horizontally, and metal-2 vertically (you may not need metal-2 for this assignment).

Be sure to use labels to identify inputs and outputs (including Vdd and GND).

First, design the parts (on paper) like we did in class, using Karnaugh maps, DeMorgan's law, and transistor symbols. Double-check the p-logic and n-logic, and show that the combined circuit will work as expected. Also show the complete circuit - redraw the top and bottom halfs connected together.

What to turn in:
You should turn in the part designs in class on the due date. The Magic files should be turned in according to the directions given on this link. Turn in your log file with the part designs, in class on the due date. Staple them together. If you do not turn in a log file, you may receive a 0 for the Magic drawings.

You may find this link useful. Keep in mind that it points to a page at the University of Southern California; while it may help you get used to magic, you must follow our directions to receive full credit.

You may use double-rail logic for the XOR gate only.