CSc 4210/6210 - Computer Architecture
Homeworks
Homeworks will be graded mainly on effort, instead of correctness.
Points may be deducted for things like being late, not stapling it
(if it is more than one page), using torn paper, using paper with
fringes, not attempting questions, and messiness.
Work out a solution to the
problem on your own.
After you get your work checked, get together with other students to see
how their answers compare.
If you are not sure what the answer should be, ask in class,
post to the discussion page, see the TA during his/her office hours, or see
the professor during his office hours. You are still expected to turn
in your own copy of the homework.
An explanation is expected for each answer. If you only provide
diagrams, you should not expect to receive points.
Use non-proprietary formats such as .txt, .pdf, .png, or .odt when turning in
the assignments.
- Due January 14 -- Refer to this diagram. Analyze it like we did with the other diagram of N and P-type transistors, and make a truth-table. What is it? Also, read this article (https://itmunch.com/future-elon-musks-neuralink/) and write a short (around 5 sentences) reaction.
- Due January 21 -- Chapter 1 problems 1, 3, and 7.
- Due January 28 -- Chapter 1 problem 5, 8, and 9.
- Due February 4 -- Chapter 1 problems 13, 16, and 20. (Hint: for number 16 consider what you would do for A, B, and C individually.) Refer to the D latch diagram given out in class. For the given clock and D signals, what is the resulting output at Q? For the D register, using the same clock and D signals, what is the resulting outputs at -QL and QR? You can use the dashed boxes shown under the given signals for your answers, though you should provide a written explanation, too.
- Due February 11 -- Chapter 2 problems 7 and 8. Revisit the previous homework's question about the D latch and D registers; would you change your answer, and if so, how? Finally, for the diagram in Figure 2-10, suppose that A3=0,A2=0,A1=1,A0=1, and "count enable"=1. What values will the flip-flops store after the next rising edge of the clock?
- Due February 18 -- Chapter 2 problem 11, Chapter 3 problem 15. Show how you would change Figure 2.11 to make Load the highest precedence signal, followed by Increment, followed by Clear.
- Due February 25 -- Chapter 4 problems 2, 10, and 15.
- Due March 3 -- Chapter 4 problems 19 and 21. Chapter 5 problem 1.
- Due March 10 -- Chapter 5 problems 2, 3, and 4.
- Due March 17 (Spring Break) -- (Spring Break)
- Due March 24 -- Chapter 5 problems 5, 6, and 10.
- Due March 31 -- Chapter 5 problems 12, 13 (XCH, SEQ, and BPA), and 15.
- Due April 7 -- Chapter 5 problems 21 and 25. Chapter 6 problem 1.
- Due April 14 -- Chapter 7 problems 2, 7, and 11.
- Due April 21 -- Chapter 7 problems 16 and 17.